The present invention relates to out-of-range detectors for analog-to-digital converters (ADC), and more particularly to a pipelined ADC.
One traditional type of ADC receives an analog input voltage to be converted into digital form at the input of a pipeline of stages. The first stage does the first, rough determination of where the analog level is, producing the most significant bit of the result. Subsequent stages further refine the determination of the value of the signal, producing additional bits in less significant positions of the answer. This type of ADC has advantages where multiple conversions are done, and can be pipelined, with multiple different values propagating through the pipeline to provide a high throughput.
A disadvantage of a pipelined ADC is where a single value needs to be determined quickly, since it needs to propagate through the pipeline. Flash architectures and bipolar technologies have been used to produce essentially a single stage ADC which can produce an answer in a single clock cycle. A disadvantage of such an architecture, however, is that for larger bit resolution values, the size and power dissipation of the circuit increases significantly.
Typically, an out-of-range (OTR) indicator is used with two comparators added to the input of the ADC in either pipelined or non-pipelined configurations. These two comparators will compare the input analog signal to the full scale positive voltage and the full scale negative voltage. If these values are exceeded, an out-of-range indication will be provided. However, to provide an accurate out-of-range indication, such a comparator must have an offset value of better than the accuracy of the least significant bit resolution of the ADC. Accordingly, highly accurate comparators are required, increasing the complexity, area, and power required for such comparators.